Semicon Shorts

Author: SemiconShorts

  • ATPG – Stuck-at and At-speed

    ATPG – Stuck-at and At-speed

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    ATPG – Automatic test Pattern Generation Used to create a set of patterns, which can test the design for the faults as discussed in DFT-Fault models article. I would recommend reading DFT-Fault models to understand this article better. Has two main steps: Generate patterns, Perform fault simulation to check which faults can be detected by…

  • DFT – Fault Models

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    DFT – Design for test is a technique that helps to tests for manufacturing or structural defects. Unlike Functional verification, which tests for the bugs/issues in the functionality of the design, DFT works to test if fabrication induced any defect in the chip. Some of the techniques of DFT are Scan, BIST, JTAG etc. The…